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POD: A Highly-Efficient 3D-Integrated
Heterogeneous Many-core Architecture
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Faculty
Hsien-Hsin Sean Lee
Graduate Students
Dong Hyuk Woo
External Collaborators
Marsha Eng (Intel Corporation)
Joshua B. Fryman (Intel Corporation)
Allan D. Knies (Intel Research Berkeley)
Sponsor
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NSF CPA
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Description
To feature hundreds or even thousands of processing cores on a single-die many-core processor, the challenges of energy consumption and performance scalability must be addressed within a given die area budget. Current commercial designs focus on MIMD-style multicores built with rather complex cores. While such designs provide a degree of generality, they may not be the most efficient way to build processors for applications with inherently scalable parallelism.
In this research, we revisit the massively parallel SIMD processing paradigm with modern process technology and present a highly efficient on-chip accelerator architecture called Parallel-On-Die (or POD). Leveraging from emerging 3D integration, POD is designed to address the key challenges of overall chip power, on-chip communication bandwidth, area limitations, and energy consumed by routers by factoring out features necessary for normal MIMD-style many-core platform and focusing on architectures that match scalable workloads. Its deterministic computation and communication model offers much better energy efficiency while also providing a fully debuggable programming environment to application developers. Our single-chip POD is capable of best-in-class scalar performance as well as extremely efficient, scalable parallel performance up to 1.5 TFLOPS of single-precision oating-point arithmetic. Our experimental results show that POD can achieve nearly linear speedup on a large number of SIMD PEs in some application domains, and this speedup is much bigger than the maximum speedup a homogeneous MIMD many-core processor can offer. Using the metric of Performance per Joule, we show that POD also improves the computation-energy efficiency substantially over a homogeneous many-core processor. Furthermore, owing to synchronized computation and communication, POD can efficiently suppress energy consumption on the novel communication method in our proposed interconnection network.
Technical Presentation
An overview slide is available here.
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Refereed Journal Articles
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| ACM TACO | Dong Hyuk Woo, Joshua B. Fryman, Allan D. Knies, and Hsien-Hsin S. Lee. "Chameleon: Virtualizing Idle Acceleration Cores of A Heterogeneous Multi-Core Processor for Caching and Prefetching." In ACM Transactions on Architecture and Code Optimization, Vol. 7, No. 1, pp.3:1-3:35, April, 2010.
[pdf] |
| IEEE Computer | Dong Hyuk Woo and Hsien-Hsin S. Lee. "Extending Amdahl's Law for Energy-Efficient Computing in the Many-Core Era." In IEEE Computer, Vol. 41, No. 12, pp.24-31, December, 2008.
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| IEEE MICRO | Dong Hyuk Woo, Joshua B. Fryman, Allan D. Knies, Marsha Eng, and Hsien-Hsin S. Lee. "POD: A 3D-Integrated Broad-Purpose Acceleration Layer." In IEEE MICRO special issue on Accelerator Architectures, Vol. 28, No. 4, pp.28-40, July/August, 2008.
[pdf] |
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Refereed Conference Papers
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| ASPLOS XV | Dong Hyuk Woo and Hsien-Hsin S. Lee. "COMPASS: A Programmable Data Prefetcher Using Idle GPU Shaders." In Proceedings of the 15th International Conference on Architectural Support for Programming Languages and Operating Systems, pp.297-309, Pittsburgh, PA, March, 2010.
[pdf] [slides] |
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Refereed Workshop Papers
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| HPEC-07 | Dong Hyuk Woo, Joshua B. Fryman, Allan D. Knies, Marsha Eng, and Hsien-Hsin S. Lee. "POD: A Parallel-On-Die Architecture." In the 11th Annual Workshop on High Performance Embedded Computing, Lexington, Massachusetts, September, 2007. (One of four finalists for the Best Paper Award.)
[pdf] [slides] |
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Technical Report
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CERCS Technical Report
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Dong Hyuk Woo, Joshua B. Fryman, Allan D. Knies, and Hsien-Hsin S. Lee. "Chameleon: Virtualizing Idle Acceleration Cores of A Heterogeneous Multi-Core Processor for Caching and Prefetching." Technical Report GIT-CERCS-08-11, Georgia Institute of Technology, December 2008
[pdf]
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CERCS Technical Report
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Dong Hyuk Woo, Joshua B. Fryman, Allan D. Knies, Marsha Eng, and Hsien-Hsin S. Lee. "POD: A Parallel-On-Die Architecture." Technical Report GIT-CERCS-07-09, Georgia Institute of Technology, May 2007
[pdf]
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100 Binney Street
Cambridge, MA 02142
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http://hsienhsinlee.github.io
650-709-9452
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