Description
More details to come.
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Refereed Journal Articles
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| IEEE MICRO | Vivek Parmer, Syed Shakib Sarwar, Ziyun Li, Hsien-Hsin S. Lee, Barbara De Salvo, Manan Suri. "Exploring Memory-Oriented Design Optimization of Edge-AI Hardware for Extended Reality Applications." In IEEE MICRO Special Issue on TinyML, Volume 43, Issue 6, 2023. |
| IEEE MICRO | Liu Ke, Xuan Zhang, Jinin So, Jong-Geon Lee, Shin-Haeng Kang, Sukhan Lee, Songyi Han, YeonGon Cho, JIN Hyun Kim, Yongsuk Kwon, KyungSoo Kim, Jin Jung, Ilkwon Yun, Sung Joo Park, Hyunsun Park, Joonho Song, Jeonghyeon Cho, Kyomin Sohn, Nam Sung Kim, and Hsien-Hsin S. Lee. "Near-Memory Processing in Action: Accelerating Personalized Recommendation with AxDIMM." In IEEE MICRO Special Issue on Processing in Memory, January/February, Vol.42, Issue 1, pp.116-127, 2022.
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| JILP | Ahmad Sharif and Hsien-Hsin S. Lee. "Data Prefetching by Exploiting Global and Local Access Patterns." In the Journal of Instruction-Level Parallelism, Volume 13, 2011, ISSN 1942-9525.
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| IEEE MICRO | Nak Hee Seong, Dong Hyuk Woo, and Hsien-Hsin S. Lee. "Security Refresh: Protect Phase-Change Memory against Malicious Wear-out." In IEEE MICRO special issue on Top Picks from the Computer Architecture Conferences of 2010, pp.119-127, January/February, 2011.
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Refereed Conference Papers
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| TinyML-23 | Vivek Parmer, Syed Shakib Sarwar, Ziyun Li, Hsien-Hsin S. Lee, Barbara De Salvo, Manan Suri. "Memory-Oriented Design Space Exploration of Edge-AI Hardware for XR Applications." In tinyML Research Symposium, 2023.
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| MICRO-47 | Jen-Cheng Huang, Joo Hwan Lee, Hyesoon Kim, and Hsien-Hsin S. Lee. "GPUMech: GPU Performance Modeling Technique based on Interval Analysis." In Proceedings of the 47th ACM/IEEE International Symposium on Microarchitecture, pp.268-279, Cambridge, UK, December, 2014.
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| ISCA-40 | Nak Hee Seong, Sungkap Yeo, and Hsien-Hsin S. Lee. "Tri-Level-Cell Phase Change Memory: Toward an Efficient and Reliable Memory System." In Proceedings of the 40th International Symposium on Computer Architecture, pp.440-451, Tel-Aviv, Israel, June, 2013.
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| ICPP | Mrinmoy Ghosh, Ripal Nathuji, Min Lee, Karsten Schwan, and Hsien-Hsin S. Lee. "Symbiotic Scheduling for Shared Caches in Multi-Core Systems Using Memory Footprint Signature." In Proceedings of the 40th IEEE International Conference on Parallel Processing, pp.11-20, Taipei, Taiwan, September, 2011.
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| MWSCAS | Dong Hyuk Woo, Nak Hee Seong, and Hsien-Hsin S. Lee. "Heterogeneous Die Stacking of SRAM Row Cache and 3-D DRAM: An Empirical Design Evaluation." In Proceedings of the 54th IEEE International Midwest Symposium on Circuits and Systems, pp.1-4, Seoul, Korea, August, 2011. (An Invited Paper)
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| MICRO-43 | Nak Hee Seong, Dong Hyuk Woo, Vijayalakshmi Srinivasan, Jude A. Rivers, and Hsien-Hsin S. Lee. "SAFER: Stuck-At-Fault Error Recovery for Memories." In Proceedings of the 43th ACM/IEEE International Symposium on Microarchitecture, pp.115-124, Atlanta, Georgia, December, 2010.
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| ISCA-37 | Nak Hee Seong, Dong Hyuk Woo, and Hsien-Hsin S. Lee. "Security Refresh: Prevent Malicious Wear-out and Increase Durability for Phase-Change Memory with Dynamically Randomized Address Mapping." In Proceedings of the 37th International Symposium on Computer Architecture, pp.383-394, Saint-Malo, France, June, 2010. (One of the 11 papers selected as IEEE MICRO's Top Picks from the Computer Architecture Conferences of 2010)
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| 3DIC | Dean L. Lewis and Hsien-Hsin S. Lee. "Architectural Evaluation of 3D Stacked RRAM Caches." In IEEE International 3D System Integration Conference, San Francisco, CA, September, 2009.
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Refereed Workshop Papers
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| IPDPSW | Lifeng Nai and Hsien-Hsin S. Lee. "Reducing False Transactional Conflicts With Speculative Sub-blocking State - An Empirical Study for ASF Transactional Memory System." In the 27th International Symposium on Parallel & Distributed Processing Workshops and PhD Forum, Boston, MA, May, 2013.
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| WDDD | Sungkap Yeo, Nak Hee Seong, and Hsien-Hsin S. Lee. "Can Multi-Level Cell PCM Be Reliable and Usable? Analyzing the Impact of Resistance Drift." In the 10th Annual Workshop on Duplicating, Deconstructing and Debunking in conjunction with the 39th International Symposium on Computer Architecture, Portland, OR, June, 2012.
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