Description
This project designs, implements, and fabricates a 3D many-core processor called
3D-MAPS (3D Massively Parallel
Processor with Stacked memory) using 3D integration technology. The objective of this
project is threefold. First, we investigate the future many-core architecture and bandwidth-limited applications with emerging
3D integration technology, which brings the processing elements and the storage closer to each other for collaborative,
high-performance execution. Secondly, using this 3D-integrated design, we intend to demonstrate the potentially immense memory
bandwidth enabled by high-density, fast die-to-die vias or through-silicon-vias (TSV), a likely front-runner solution for
future many-core processors.
In addition, the entire research team aims to figure out how to incorporate current commercially available 2D design and analysis tools
and existing test methodology, and then leverage them for 3D-IC design with minimal add-on's and cost required.
This project involves three faculty and more than a dozen of graduate students with our partner foundary and sponsors.
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Refereed Journal Articles
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| IEEE TC | Dae Hyun Kim, Krit Athikulwongse, Michael B. Healy, Mohammad M. Hossain, Moongon Jung, Ilya Khorosh, Gokul Kumar, Young-Joon Lee, Dean L. Lewis, Tzu-Wei Lin, Chang Liu, Shreepad Panth, Mohit Pathak, Minzhen Ren, Guanhao Shen, Taigon Song, Dong Hyuk Woo, Xin Zhao, Joungho Kim, Ho Choi, Gabriel H. Loh, Hsien-Hsin S. Lee, and Sung Kyu Lim. "Design and Analysis of 3D-MAPS 3D Massively Parallel Processor with Stacked Memory." In IEEE Transactions on Computers, Vol. 64, No.1, pp.112-125, January, 2015.
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| IEEE TVLSI | Dong Hyuk Woo, Nak Hee Seong, and Hsien-Hsin S. Lee. "Pragmatic Integration of An SRAM Row Cache in Heterogeneous 3-D DRAM Architecture using TSV." In IEEE Transactions on Very Large Scale Integration Systems, Vol.21, No.1, pp.1-13, January, 2013.
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| IEEE D&T | Hsien-Hsin S. Lee and Krishnendu Chakrabarty. "Test Challenges for 3D Integrated Circuits." In IEEE Design & Test of Computers, Special Issue on 3D IC Design and Test, Vol.26, Issue 5, pg. 26-35, Sept/Oct, 2009.
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| IEEE MICRO | Dong Hyuk Woo, Joshua B. Fryman, Allan D. Knies, Marsha Eng, and Hsien-Hsin S. Lee. "POD: A 3D-Integrated Broad-Purpose Acceleration Layer." In IEEE MICRO special issue on Accelerator Architectures, Vol. 28, No. 4, pp.28-40, July/August, 2008.
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| IEEE TCAD | Michael Healy, Mario Vittes, Mongkol Ekpanyapong, Chinnakrishnan Ballapuram, Sung Kyu Lim, Hsien-Hsin S. Lee, and Gabriel H. Loh. "Multi-Objective Microarchitectural Floorplanning For 2D and 3D ICs." In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 26, No. 1, pp.38-52, 2007.
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Refereed Conference Papers
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| DATE-2017 | Tianjian Li, Yan Han, Xiaoyao Liang, Hsien-Hsin S. Lee, and Li Jiang. "Fault Clustering Technique for 3D Memory BISR." In Proceedings of the 2017 Design, Autoation and Test in Europe Conference and Exhibition (DATE), Lausanne, Switzerland, March, 2017.
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| ISSCC | Dae Hyun Kim, Krit Athikulwongse, Michael B. Healy, Mohammad M. Hossain, Moongon Jung, Ilya Khorosh, Gokul Kumar, Young-Joon Lee, Dean L. Lewis, Tzu-Wei Lin, Chang Liu, Shreepad Panth, Mohit Pathak, Minzhen Ren, Guanhao Shen, Taigon Song, Dong Hyuk Woo, Xin Zhao, Joungho Kim, Ho Choi, Gabriel H. Loh, Hsien-Hsin S. Lee, and Sung Kyu Lim. "3D-MAPS: 3D Massively Parallel Processor with Stacked Memory." In Technical Digest of the IEEE International Solid-State Circuits Conference, pp.188-190, San Francisco, CA, 2012.
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| 3DIC | Xiaodong Wang, Dilip Vasudevan, and Hsien-Hsin S. Lee. "Global Built-In Self-Repair for 3-D Memories with Redundancy Sharing and Parallel Testing." In Proceedings of the IEEE International 3D System Integration Conference, Osaka, Japan, 2012.
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| ICCD | Dean L. Lewis, Shreepad Panth, Xin Zhao, Sung Kyu Lim, and Hsien-Hsin S. Lee. "Designing 3D Test Wrappers for Pre-bond and Post-bond Test of 3D Embedded Cores." In Proceedings of the XXIX IEEE International Conference on Computer Design, pp.90-95, University of Massachusetts, Amherst, USA, October, 2011.
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| MWSCAS | Dong Hyuk Woo, Nak Hee Seong, and Hsien-Hsin S. Lee. "Heterogeneous Die Stacking of SRAM Row Cache and 3-D DRAM: An Empirical Design Evaluation." In Proceedings of the 54th IEEE International Midwest Symposium on Circuits and Systems, pp.1-4, Seoul, Korea, August, 2011. (An Invited Paper)
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| CICC | Michael B. Healy, Krit Athikulwongse, Rohan Goel, Mohammad M. Hossain, Dae Hyun Kim, Young-Joon Lee, Dean L. Lewis, Tzu-Wei Lin, Chang Liu, Moongon Jung, Brian Ouellette, Mohit Pathak, Hemant Sane, Guanhao Shen, Dong Hyuk Woo, Xin Zhao, Gabriel H. Loh, Hsien-Hsin S. Lee, and Sung Kyu Lim. "Design and Analysis of 3D-MAPS: A Many-Core 3D Processor with Stacked Memory." In Proceedings of the IEEE Custom Integrated Circuits Conference, San Jose, California, September, 2010. (Intel/CICC Student Scholarship Award)
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| HPCA-16 | Dong Hyuk Woo, Nak Hee Seong, Dean L. Lewis, and Hsien-Hsin S. Lee. "An Optimized 3D-Stacked Memory Architecture by Exploiting Excessive, High-Density TSV Bandwidth." In Proceedings of the 16th International Symposium on High-Performance Computer Architecture, pp.429-440, Bangalore, India, January, 2010.
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| ICCAD | Xin Zhao, Dean L. Lewis, Hsien-Hsin S. Lee, and Sung Kyu Lim. "Pre-bond Testable Low-Power Clock Tree Design for 3D Stacked ICs." In Proceedings of the 2009 International Conference on Computer-Aided Design, pp.184-190, San Jose, CA, November, 2009. (Nominated for the Best Paper Award by ICCAD-09)
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| 3DIC | Dean L. Lewis and Hsien-Hsin S. Lee. "Architectural Evaluation of 3D Stacked RRAM Caches." In IEEE International 3D System Integration Conference, San Francisco, CA, September, 2009.
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| ISVLSI | Dean L. Lewis and Hsien-Hsin S. Lee. "Testing Circuit-Partitioned 3D IC Designs." In IEEE Computer Society Annual Symposium on VLSI, Tampa, FL, May, 2009.
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| ISVLSI | Dean L. Lewis, Sudhakar Yalamanchili, and Hsien-Hsin S. Lee. "High Performance Non-blocking Switch Design in 3D Die-Stacking Technology." In IEEE Computer Society Annual Symposium on VLSI, Tampa, FL, May, 2009.
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| MICRO-40 | Mrinmoy Ghosh and Hsien-Hsin S. Lee. "Smart Refresh: An Enhanced Memory Controller Design for Reducing Energy in Conventional and 3D Die-Stacked DRAMs." In Proceedings of the 40th ACM/IEEE International Symposium on Microarchitecture, pp.134-145, Chicago, IL, December, 2007.
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| ITC-07 | Dean L. Lewis and Hsien-Hsin S. Lee. "A Scan-Island Based Design Enabling Pre-bond Testability in Die-Stacked Microprocessors." In Proceedings of the International Test Conference, Santa Clara, CA, October, 2007.
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Refereed Workshop Papers
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| 3D-TEST | Dean Lewis, Michael Healy, Mohammad Hossain, Tzu-Wei Lin, Mohit Pathak, Hemant Sane, Sung Kyu Lim, Gabriel Loh, and Hsien-Hsin S. Lee. "Design and test of 3D-MAPS, a 3D Die-Stack Many-Core Processor." In the first IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits (poster), Austin, Texas, November, 2010.
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| 3D Integration | Dean L. Lewis and Hsien-Hsin S. Lee. "Test Strategies for 3D Die Stacked Integrated Circuits." In Workshop on 3D Integration --- Technology, Architecture, Design, Automation, and Test in conjunction with Design, Automation and Test in Europe (DATE-09), Nice, France, April, 2009.
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