All Refereed Papers
|
| IEEE TC | Dae Hyun Kim, Krit Athikulwongse, Michael B. Healy, Mohammad M. Hossain, Moongon Jung, Ilya Khorosh, Gokul Kumar, Young-Joon Lee, Dean L. Lewis, Tzu-Wei Lin, Chang Liu, Shreepad Panth, Mohit Pathak, Minzhen Ren, Guanhao Shen, Taigon Song, Dong Hyuk Woo, Xin Zhao, Joungho Kim, Ho Choi, Gabriel H. Loh, Hsien-Hsin S. Lee, and Sung Kyu Lim. "Design and Analysis of 3D-MAPS 3D Massively Parallel Processor with Stacked Memory." In IEEE Transactions on Computers, Vol. 64, No.1, pp.112-125, January, 2015.
[pdf] |
| IEEE TVLSI | Dong Hyuk Woo, Nak Hee Seong, and Hsien-Hsin S. Lee. "Pragmatic Integration of An SRAM Row Cache in Heterogeneous 3-D DRAM Architecture using TSV." In IEEE Transactions on Very Large Scale Integration Systems, Vol.21, No.1, pp.1-13, January, 2013.
[pdf] |
| ISSCC | Dae Hyun Kim, Krit Athikulwongse, Michael B. Healy, Mohammad M. Hossain, Moongon Jung, Ilya Khorosh, Gokul Kumar, Young-Joon Lee, Dean L. Lewis, Tzu-Wei Lin, Chang Liu, Shreepad Panth, Mohit Pathak, Minzhen Ren, Guanhao Shen, Taigon Song, Dong Hyuk Woo, Xin Zhao, Joungho Kim, Ho Choi, Gabriel H. Loh, Hsien-Hsin S. Lee, and Sung Kyu Lim. "3D-MAPS: 3D Massively Parallel Processor with Stacked Memory." In Technical Digest of the IEEE International Solid-State Circuits Conference, pp.188-190, San Francisco, CA, 2012.
[pdf] [slides] |
| MWSCAS | Dong Hyuk Woo, Nak Hee Seong, and Hsien-Hsin S. Lee. "Heterogeneous Die Stacking of SRAM Row Cache and 3-D DRAM: An Empirical Design Evaluation." In Proceedings of the 54th IEEE International Midwest Symposium on Circuits and Systems, pp.1-4, Seoul, Korea, August, 2011. (An Invited Paper)
[pdf] [slides] |
| IEEE MICRO | Nak Hee Seong, Dong Hyuk Woo, and Hsien-Hsin S. Lee. "Security Refresh: Protect Phase-Change Memory against Malicious Wear-out." In IEEE MICRO special issue on Top Picks from the Computer Architecture Conferences of 2010, pp.119-127, January/February, 2011.
[pdf] |
| MICRO-43 | Nak Hee Seong, Dong Hyuk Woo, Vijayalakshmi Srinivasan, Jude A. Rivers, and Hsien-Hsin S. Lee. "SAFER: Stuck-At-Fault Error Recovery for Memories." In Proceedings of the 43th ACM/IEEE International Symposium on Microarchitecture, pp.115-124, Atlanta, Georgia, December, 2010.
[pdf] [slides] |
| CICC | Michael B. Healy, Krit Athikulwongse, Rohan Goel, Mohammad M. Hossain, Dae Hyun Kim, Young-Joon Lee, Dean L. Lewis, Tzu-Wei Lin, Chang Liu, Moongon Jung, Brian Ouellette, Mohit Pathak, Hemant Sane, Guanhao Shen, Dong Hyuk Woo, Xin Zhao, Gabriel H. Loh, Hsien-Hsin S. Lee, and Sung Kyu Lim. "Design and Analysis of 3D-MAPS: A Many-Core 3D Processor with Stacked Memory." In Proceedings of the IEEE Custom Integrated Circuits Conference, San Jose, California, September, 2010. (Intel/CICC Student Scholarship Award)
[pdf] |
| ISCA-37 | Nak Hee Seong, Dong Hyuk Woo, and Hsien-Hsin S. Lee. "Security Refresh: Prevent Malicious Wear-out and Increase Durability for Phase-Change Memory with Dynamically Randomized Address Mapping." In Proceedings of the 37th International Symposium on Computer Architecture, pp.383-394, Saint-Malo, France, June, 2010. (One of the 11 papers selected as IEEE MICRO's Top Picks from the Computer Architecture Conferences of 2010)
[pdf] [slides] |
| ACM TACO | Dong Hyuk Woo, Joshua B. Fryman, Allan D. Knies, and Hsien-Hsin S. Lee. "Chameleon: Virtualizing Idle Acceleration Cores of A Heterogeneous Multi-Core Processor for Caching and Prefetching." In ACM Transactions on Architecture and Code Optimization, Vol. 7, No. 1, pp.3:1-3:35, April, 2010.
[pdf] |
| ASPLOS XV | Dong Hyuk Woo and Hsien-Hsin S. Lee. "COMPASS: A Programmable Data Prefetcher Using Idle GPU Shaders." In Proceedings of the 15th International Conference on Architectural Support for Programming Languages and Operating Systems, pp.297-309, Pittsburgh, PA, March, 2010.
[pdf] [slides] |
| HPCA-16 | Dong Hyuk Woo, Nak Hee Seong, Dean L. Lewis, and Hsien-Hsin S. Lee. "An Optimized 3D-Stacked Memory Architecture by Exploiting Excessive, High-Density TSV Bandwidth." In Proceedings of the 16th International Symposium on High-Performance Computer Architecture, pp.429-440, Bangalore, India, January, 2010.
[pdf] [slides] |
| ACM OSR | Dong Hyuk Woo and Hsien-Hsin S. Lee. "PROPHET: Goal-Oriented Provisioning for Highly Tunable Multicore Processors in Cloud Computing." In ACM SIGOPS Operating Systems Review special issue on the Interaction among the OS, Compilers, and Multicore Processors, Vol. 43, No. 2, pp.102-103, April, 2009.
[pdf] |
| IEEE Computer | Dong Hyuk Woo and Hsien-Hsin S. Lee. "Extending Amdahl's Law for Energy-Efficient Computing in the Many-Core Era." In IEEE Computer, Vol. 41, No. 12, pp.24-31, December, 2008.
[pdf] |
| IEEE MICRO | Dong Hyuk Woo, Joshua B. Fryman, Allan D. Knies, Marsha Eng, and Hsien-Hsin S. Lee. "POD: A 3D-Integrated Broad-Purpose Acceleration Layer." In IEEE MICRO special issue on Accelerator Architectures, Vol. 28, No. 4, pp.28-40, July/August, 2008.
[pdf] |
| HPEC-07 | Dong Hyuk Woo, Joshua B. Fryman, Allan D. Knies, Marsha Eng, and Hsien-Hsin S. Lee. "POD: A Parallel-On-Die Architecture." In the 11th Annual Workshop on High Performance Embedded Computing, Lexington, Massachusetts, September, 2007. (One of four finalists for the Best Paper Award.)
[pdf] [slides] |
| CMPMSI | Dong Hyuk Woo and Hsien-Hsin S. Lee. "Analyzing Performance Vulnerability due to Resource Denial-of-Service Attack on Chip Multiprocessors." In Workshop on Chip Multiprocessor Memory Systems and Interconnects in conjunction with the 13th International Conference on High-Performance Computer Architecture, Phoenix, Arizona, February, 2007.
[pdf] [slides] |
| CASES-06 | Dong Hyuk Woo, Mrinmoy Ghosh, Emre Özer, Stuart Biles, and Hsien-Hsin S. Lee. "Reducing Energy of Virtual Cache Synonym Lookup using Bloom Filters." In Proceedings of the ACM/IEEE International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, pp.179-189, Seoul, Korea, October, 2006.
[pdf] [slides] |
|
Ph.D. Dissertation
|
| Dong Hyuk Woo. "Designing Heterogeneous Many-Core Processors to Provide High Performance under Limited Chip Power Budget." School of Electrical and Computer Engineering, Georgia Institute of Technology, 2010.
[pdf] |
|
|
